1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device with capacitor electrodes and a manufacturing method thereof.
2. Description of the Background Art
Conventionally a DRAM (Dynamic Random Access Memory) as one of the semiconductor devices is known. FIG. 9 is a schematic cross section view showing a semiconductor device according to a prior art. The semiconductor device according to a prior art is described with reference to FIG. 9.
Referring to FIG. 9, the semiconductor device is a DRAM which includes a field effect transistor and a capacitor formed on a semiconductor substrate 101. The capacitor stores an electric charge as a memory signal. And the field effect transistor works as a switching element which controls the storage of the electric charge to the capacitor. Conductive regions 102a to 102e are formed in the main surface of the semiconductor substrate 101 with gaps between the regions. The conductive regions 102a to 102d become source and drain regions of the field effect transistors. A gate insulating film 103a to 103c is formed on the semiconductor substrate 101 above the channel regions located between the conductive regions 102a to 102d. Gate electrodes 104a to 104c are formed on the gate insulating film 103a to 103c. A side wall insulating film 105a to 105f is formed on the side walls of the gate electrodes 104a to 104c. A coating insulating film 106a to 106c is formed on the gate electrodes 104a to 104c. A field effect transistor is formed of the gate electrode 104a, the gate insulating film 103a and conductive regions 102a and 102b as the source and drain regions, respectively. Another field effect transistor is formed of the gate electrode 104b, the gate insulating film 103b and the conductive regions 102b and 102c as the source and drain regions, respectively. Still another field effect transistor is formed of the gate electrode 104c, the gate insulating film 103c and the conductive regions 102c and 102d as the source and drain regions, respectively.
The first interlayer insulating film 107 is formed on the coating insulating film 106a to 106c, the side wall insulating film 105a to 105f and the main surface of the semiconductor substrate 101. Contact holes 108a and 108b are formed in the regions located above the conductive regions 102b and 102c in the first interlayer insulating film 107. Conductive material film 109a and 109b, such as a doped polysilicon film, is filled in inside the contact holes 108a and 108b. The second interlayer insulating film 110 is formed on the first interlayer insulating film 107. A contact hole 111a is formed in the second interlayer insulating film 110 in the regions located above the conductive material film 109b. In addition, a contact hole 111b is formed in the region located above the conductive region 102e in the main surface of the semiconductor substrate 101 by removing part of the first and the second interlayer insulating films 107 and 110. A conductive material film 115a and 115b, such as a tungsten film, is filled in inside of the contact holes 111a and 111b, respectively. The first wiling layers 112a and 112b are formed on the conductive material film 115a and 115b, respectively.
The third interlayer insulating film 113 is formed on the first wiling layer 112a and 112b and the second interlayer insulating film 110. A contact hole 114 is formed in the reference located above the conductive material film 109a by removing part of the second and of the third interlayer insulating films 110 and 113. A conductive material film 116 is filled in inside of the contact hole 114.
The fourth interlayer insulating film 117 is formed on the third interlayer insulating film 113. A contact hole 150 is formed in the region located above the first wiring layer 112b by removing part of the third and the fourth interlayer insulating films 113 and 117. A conductive material film 151 is filled in inside of the contact hole 150.
The fifth interlayer insulating film 118 is formed on the fourth interlayer insulating film 117. An aperture part 119 is formed in the regions located above the conductive material film 116 by removing part of the fourth and the fifth interlayer insulating film 117 and 118. A capacitor lower electrode 120 which is connected to the conductive material film 116 is formed inside of the aperture part 119. A dielectric film 121 is formed so as to extend from the capacitor lower electrode 120 to the upper surface of the fifth interlayer insulating film 118. A capacitor upper electrode 122 is formed on the dielectric film 121 so as to fill in the inside of the aperture part 119 and to extend over the upper surface of the fifth interlayer insulating film 118. A capacitor is formed of the capacitor lower electrode 120, the dielectric film 121 and the capacitor upper electrode 122.
The sixth interlayer insulating film 123 is formed on the capacitor upper electrode 122 and the fifth interlayer insulating film 118. A contact hole 152a is formed in the region located above the capacitor upper electrode 122 of the sixth interlayer insulating film 123. A contact hole 152b is formed in the region located above the conductive material film 151 by removing part of the fifth and the sixth interlayer insulating films 118 and 123. A conductive material film 153a and 153b, such as a tungsten film, is filled in inside of the contact holes 152a and 152b. The conductive material film 153a is connected to the capacitor upper electrode 122. The conductive material film 153b is connected to the conductive material film 151. The second wiring layer 154a and 154b, made of aluminum or the like, is formed on the conductive material film 152a and 152b. The second wiring layer 154a is utilized to fix the potential of the capacitor upper electrode 122. In a semiconductor device such as a DRAM, as shown in FIG. 9, a plurality of memory cells with capacitors are arranged in a matrix form on the substrate 101. Then, an interlayer insulating film (not shown) is formed on the second wiring layer 154a and 154b. 
As for semiconductor devices as represented by DRAM the demand for miniaturization and high levels of integration continues to grow strongly. Therefore, the size of a memory cell of a DRAM as shown in FIG. 9 is becoming smaller and smaller. However, it is necessary to store a specific amount of electric charge in a capacitor which stores an electric charge in a memory cell. Therefore, capacitor structures which are in the form of extending in the vertical direction, such as a cylindrical type capacitor as shown in the figures or a thick film type capacitor, have been adopted for the purpose of securing the capacitance of the capacitors while making the size of the memory cells smaller. On the other hand, it is necessary to connect the first wiring 112b, which is connected to the conductive region 102e, with the second wiling layer 154b via the contact holes 152b and 150 for the purpose of supplying a signal to, or of fixing the potential of, the conductive region 102e, or the like, which is located below the capacitor upper electrode 122. At this time, the contact hole 152a, located above the capacitor upper electrode 122, and the contact hole 152b, located below the second wiring layer 154b, have different depths due to the structure of the capacitor. Thereby, in the case that those contact holes 152a and 152b are formed in one etching step, it is necessary to continue the etching until the contact hole 152b achieves a predetermined depth. At this time, the capacitor upper electrode 122 undergoes excessive etching at the bottom of the contact hole 152a. As a result of this, the problem arises that the capacitor upper electrode 122 receives damage or the contact hole 152a penetrates the capacitor upper electrode 122. Therefore, conventionally the etching step of forming the contact hole 152a and the etching step of forming the contact hole 152b are carried out separately. As a result of this, the number of steps for a process of the semiconductor device has increased and this becomes the cause of increased manufacturing cost of a semiconductor device.
In addition, overlapping mask errors in the lithography process for forming the second wiring layer 154a and 154b and the lithography process for forming contact holes 152a and 152b make the positions of the second wiring layer 154a and 154b and the contact holes 152a and 152b shift. In this case, the second wiring layer 154a and the capacitor upper electrode 122 are not connected and, therefore, defects occur in the semiconductor device.
In addition, together with the miniaturization of semiconductor devices the wiring width, the wiling height (section area of the wiring) and the gap between wires of the second wiling layer 154a and 154b need to be made smaller. However, as the section area of wires becomes smaller in this way the wire resistance of the second wiring layer 154a and 154b increases. Such an increase of the wire resistance leads to a wiling delay. As a result of this some necessary characteristics, such as operational speed, fail to be achieved in the semiconductor device and, in some cases, defects nonetheless occur.